A method for manufacturing a liquid crystal display panel having a gate line with at least one opening

ABSTRACT

A liquid crystal display panel (and a method for manufacturing the liquid crystal display panel) includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention generally relates to a liquid crystaldisplay (LCD) panel and a method for manufacturing the same, and moreparticularly to a structure of a gate line and to an intersectionportion of the gate line and a signal line.

[0003] 2. Description of the Related Art

[0004] A conventional method for manufacturing an a-Si TFT liquidcrystal display panel is described herein below with regard to a liquidcrystal device portion. As shown in FIGS. 12(a) and 12(b), a gateelectrode 4 and a gate line 5 connected thereto are first formed into apredetermined shape on a glass substrate 2 by a conventional technique.Then, as shown in FIG. 13, a gate insulating film 6, a channel layer 8and a SiN_(x) film 10, serving as an etching stopper layer, aresuccessively stacked on the entire surface of the glass substrate 2. Asshown in FIGS. 14(a) to 14(c), after coating a resist on the SiN_(x)film 10, the glass substrate 2 is exposed to light from its back surfaceside by using the gate electrode 4 having a predetermined shape as alight shielding mask. Subsequently, the glass substrate 2 is subjectedto stepper exposure from its front surface side by using a reticle, andthen the resist is developed. Thereafter, the SiN_(x) film 10, otherthan a portion functioning as an etching stopper (e.g., channelprotecting film) 12, is etched with diluted hydrofluoric (HF) acid, andthen the resist is removed.

[0005] As described above, the etching stopper 12 can be formed througha single exposing step in which the glass substrate 2 is subjected tothe stepper exposure from its front surface side by using a reticle.However, in this conventional manufacturing method, the etching stopper12 is formed through a two-stage exposure. The stages include exposingthe substrate 2 to light from its back surface side and exposing thesubstrate 2 to light from its front surface side.

[0006] This approach is used because, when the etching stopper 12 isformed through a single-stage exposing step in which the glass substrate2 is exposed to light from its front surface side, the alignment withthe gate electrode 4 tends to be shifted and cannot be stabilized.

[0007] In contrast, if the gate electrode 4 is effectively used in thetwo-stage exposing step, the etching stopper 12 is disposed at thecenter of the gate electrode 4 in a self-aligned manner. Referring toFIG. 15, this provides a source electrode 26 and a drain electrode 28symmetrically positioned about the gate electrode 4, and also reducesoverlap areas between the gate electrode 4 and the drain electrode 28and between the gate electrode 4 and the source electrode 26. Thus, thetwo-stage exposure can improve a transistor's characteristic.

[0008] However, in manufacturing a liquid crystal display panel, thereare many complicated, time-consuming steps. Therefore, reducing thenumber of processes not only improves productivity, but also reduces themanufacturing cost of a LCD panel in which the process cost accounts fora large proportion of the total cost.

[0009] After being developed, the resist for forming the etching stopper12 has a size of approximately 20×10 μm per pixel, and such rectangularresists are arranged side-by-side over the entire surface of an arraysubstrate. Since the area of each resist is relatively small, itsadhesion to the underlying nitride film (e.g., the SiN_(x) film) is low,and hence, the resist is apt to be easily peeled-off. When the resist ispeeled-off, the etching stopper 14 cannot be properly formed, whichleads to transistor failure.

[0010] When the etching stopper layer 10 is etched with dilutedhydrofluoric acid, the etching stopper layer 10 is generally over-etchedso as not to leave an insufficiently etched portion. However, excessiveoveretching causes the side surface of the etching stopper 12 to beinclined inward at the foot thereof, thereby resulting in the formationof a “concavity” 15 (which is hidden in a top view), as shown in FIG.14(c). When films (and/or foreign matter) to be deposited in subsequentsteps are attached to the concavity 15, they cannot be removed throughcleaning and etching. As a result, as shown in FIG. 15, a leakagecurrent flows between the source electrode 26 and the drain electrode 28formed on the etching stopper 12, which leads to a leakage failure ofthe transistor.

[0011] In an attempt to overcome the above disadvantages, in JapanesePatent Application No. 10-278689 the present inventors developed a novelmethod for manufacturing a liquid crystal display panel, which includesa single exposing step by using a gate electrode and a gate line asshielding masks.

[0012] However, in the above manufacturing method, the etching stopperlayer 12 is not removed from an intersection portion of the gate linewhere the gate line and the signal line intersect each other. If theetching stopper layer is not removed from the intersection portion,etching solution may easily penetrate into the intersection portionduring an etching process, and thus an open defect of the signal linemay be latently induced.

SUMMARY OF THE INVENTION

[0013] In view of the foregoing and other problems, drawbacks, anddisadvantages of the conventional methods, it is an object of thepresent invention to provide a structure and method for removing anetching stopper layer on an intersection portion of a gate line wherethe gate line and a signal line intersect each other without using anadditional exposing step.

[0014] It is another object of the present invention that an etchingstopper be formed through only a single exposing step by using a gateelectrode and a gate line as shielding masks in the method formanufacturing a liquid crystal display panel. Reducing of the number ofsteps, especially the number of exposing steps, contributes toproductivity improvements and a reduction of the manufacturing cost.

[0015] In a first aspect, a liquid crystal display panel according tothe present invention includes two or more conductive portions and oneor more opening portions on an intersection portion of a gate line wherethe gate line and a signal line intersect each other. The gate line andthe signal line output electrical signals to a liquid crystal devicearranged in a matrix pattern. Since the etching stopper layer is removedfrom the intersection portion having opening portions, penetration ofthe etching solution (e.g., which would lead to a break in the signalline formed on the intersection portion) can be prevented.

[0016] In a second aspect, a method for manufacturing a liquid crystaldisplay panel according to the present invention includes forming a gateinsulating film, a channel layer and an etching stopper layer on atransparent substrate bearing a gate electrode and the gate line, andexposing the substrate to light from its back surface side by using thegate electrode and the gate line as light shielding masks by aphotolithography technique. Then, the resist is developed and theetching stopper layer is etched, and thereby an etching stopper isformed. Thus, the inventive manufacturing method forms an etchingstopper using a single-stage exposing step.

[0017] Further, two or more conductive portions and one or more openingportions are formed on the intersection portion of the gate line wherethe gate line and the signal line intersect each other, and the resistis removed from the opening portion. During the etching step of formingthe etching stopper layer, since the etching stopper layer is alsoetched from the opening portion side, and since the etching stopperlayer near (e.g., adjacent) the opening portion is also etched by theside-etching effect, the etching stopper layer is removed from theintersection portion.

[0018] In the liquid crystal display panel and the method formanufacturing the same according to the present invention, the exposingstep of forming the etching stopper layer includes only one step inwhich the gate electrode and the gate line are used as shielding masks.Since the inventive manufacturing method does not include atime-consuming exposing step in which a shielding mask, such as areticle, is used and a high precision positioning of the shielding maskis required, productivity is dramatically increased.

[0019] The present disclosure relates to subject matter contained inJapanese Patent Application No. 11-034227, filed Feb. 12, 1999, which isexpressly incorporated herein by reference in its entirety.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0021] FIGS. 1(a) and 1(b) are an enlarged plan view and an enlargedsectional view, respectively, illustrating a procedure for forming agate electrode in the method for manufacturing a liquid crystal displaypanel according to the present invention;

[0022]FIG. 2 is an enlarged sectional view illustrating a major part ofa procedure for forming a gate insulating film, a channel layer and anetching stopper layer;

[0023] FIGS. 3(a) and 3(b) are an enlarged plan view and an enlargedsectional view, respectively, illustrating a procedure for forming anetching stopper;

[0024]FIG. 4 is an enlarged sectional view illustrating a procedure forforming a source/drain layer;

[0025] FIGS. 5(a) to 5(d) are views illustrating a procedure forprocessing the source/drain layer, with FIG. 5(a) being an enlarged planview, FIG. 5(b) being an enlarged sectional view, FIG. 5(c) being asectional view taken on line c-c of FIG. 5(b), and FIG. 5(d) being asectional view of a storage capacity portion and a pad portion;

[0026]FIG. 6 is an enlarged perspective view showing a liquid crystaldevice portion formed with the procedure of FIGS. 5(a) to 5(d);

[0027]FIG. 7 is an enlarged plan view illustrating a procedure forforming a transparent conductive film;

[0028]FIG. 8 is an enlarged plan view illustrating a procedure forforming a signal line;

[0029]FIG. 9(a) is an enlarged sectional view of the procedure shown inFIG. 8, and FIG. 9(b) is an enlarged sectional view illustrating anintersection portion of a gate line and a signal line;

[0030]FIG. 10 is an enlarged perspective view of the liquid crystaldevice portion shown in FIG. 8;

[0031] FIGS. 11(a) to 11(c) are enlarged plan views illustrating anotherembodiment of the intersection portion of the gate line;

[0032]FIG. 12(a) and FIG. 12(b) are an enlarged plan view and anenlarged sectional view, respectively, illustrating a procedure forforming a gate electrode in a conventional method for manufacturing aliquid crystal display panel;

[0033]FIG. 13 is an enlarged sectional view illustrating a procedure forforming a gate insulating film, a channel layer and an etching stopperlayer in a conventional method for forming a liquid crystal displaypanel;

[0034] FIGS. 14(a) to 14(c) are diagrams illustrating a procedure forforming the etching stopper in a conventional method for forming aliquid crystal display panel, with FIG. 14(a) being an enlarged planview, FIG. 14(b) being an enlarged sectional view, and FIG. 14(c) beingan explanatory enlarged perspective view of the etching stopper; and

[0035]FIG. 15 is an enlarged perspective view of a liquid crystal deviceportion manufactured by the conventional method.

DETAILED DESCRIPTION OF PREFERRED Embodiments of the Invention

[0036] Referring now to the drawings, and more particularly to FIGS.1-11(c), in which only a portion corresponding to one pixel is shown forsimplification, a preferred embodiment of the liquid crystal displaypanel and the method for manufacturing the same will be described.

[0037] As shown in FIGS. 1(a) and 1(b), a gate electrode 4 and a gateline 5 connected thereto are first formed on a transparent substrate 2.The most preferable transparent substrate includes a glass substrate,but a resin substrate or a flexible substrate can be used provided it istransparent and, in particular, has good heat-resistance.

[0038] The gate electrode 4 and the gate line 5 include one or morelayers of at least one element selected from the group consisting ofMoW, Cr, Cu, Ni, Al, Mo, Ag and the like. Preferably, the gate electrode4 and the gate line 5 have excellent conductivity, excellent adhesion tothe transparent substrate 2, and more preferably, have a property suchthat atoms and molecules of the electrode material are not diffused intoa gate insulating film 6 to be formed thereon. Also, the gate electrode4 and the gate line 5 are formed on the entire surface of thetransparent substrate 2 by evaporating a specified metal or by adheringa metal foil.

[0039] After the resultant substrate 2 is coated with a photoresist, andsubsequently subjected to stepper exposure by using a reticle, theresist is developed. Subsequently, after the metal layer other than aportion functioning as the gate electrode 4 and the gate line 5 isremoved through a plasma etching procedure, the photoresist is removedto obtain the gate electrode 4 and the gate line 5.

[0040] Then, two rectangular slit-shaped opening portions 5 b are formedon the portion (e.g., intersection portion) 5 a of the gate line 5 wherethe gate line and the signal line intersect each other through aninsulating layer described below.

[0041] The opening portions 5 b have widths and sizes such that theresist applied thereto can be removed in the developing step, and thatthe etching stopper layer can be removed by being wet-etched. Conductiveportions of the gate line 5 on the intersection portion 5 a have widthssuch that the etching stopper layer on the conductive portions (e.g., onthe intersection portion of the gate line 5) can be removed almostcompletely by side-etching.

[0042] This results from wet-etching the etching stopper layer on theopening portions 5 b, without enlarging the conduction resistance of thegate line 5. In addition, and preferably, the conductive portions of thegate line 5 on the intersection portion 5 a have sizes such thatexcessive overetching is not necessary.

[0043] Next, as shown in FIG. 2, a gate insulating film 6, a channellayer 8 and an etching stopper layer 10 are successively formed in thatorder on the entire transparent substrate 2 having a gate electrode 4and a gate line 5. The gate insulating film 6 is preferably made of oneor more layers of one or more materials.

[0044] Specifically, SiO_(x) and SiN_(x) are preferably used as amaterial for the gate insulating film 6, and more preferably, a SiO_(x)film 6 a is formed on the transparent substrate 2 side and a SiN_(x)film 6 b is formed on the SiO_(x) film 6 a. The SiN_(x) film 6 bimproves adhesion of the channel layer 8 to be formed thereon. Amorphoussilicon (a-Si) is preferably used for the channel layer 8, and SiN_(x)is preferably used as the material for the etching stopper layer 10 tobe formed thereon. All of these layers are formed by conventionaltechniques.

[0045] Then, after the photoresist (not shown) is applied to the etchingstopper layer 10, the transparent substrate 2 is exposed to light byusing the gate electrode 4 and the gate line 5 as light shielding masksfrom its back surface side (e.g., the surface side not bearing theetching stopper layer 10 and the like). After the photoresist isdeveloped, a part of the photoresist which is substantially the sameshape as the gate electrode 4 and the gate line 5 is left on the gateelectrode 4 and the gate line 5. At this time, holes having the sameshape as the opening portions 5 b are formed on the photoresist on theintersection portion 5 a of the gate line 5 by the developing step.

[0046] Referring to FIGS. 3(a) and 3(b), after a heat-treatment of thephotoresist, only the etching stopper layer 10 is wet-etched and theetching stopper 12, having substantially the same shape as thephotoresist (e.g., substantially the same shape as the gate electrode 4and gate line 5) are formed. However, the etching stopper 12 is removedfrom the intersection portion 5 a, on which the opening portions 5 b areformed, by being side-etched from the width direction (e.g.,side-etching effect).

[0047] As shown in FIG. 4, after removing the photoresist, asource/drain layer 14 is formed on the transparent substrate 2 bearingthe etching stopper 12. The material for the source/drain layer 14 is ann⁺ type a-Si, and is used for attaining ohmic contact with asource/drain electrode to be formed thereon. After forming thesource/drain layer 14, a photoresist is applied to the resultantsubstrate 2.

[0048] As shown in FIGS. 5(a) to 5(d), the resultant substrate 2 issubjected to stepper exposure using a reticle having a masksubstantially the same shape as the signal line (24), including thesource/drain electrode under layer 16, and followed by plasma etching.Through the plasma etching, the source/drain layer 14, the etchingstopper 12, the channel layer 8 and the SiN_(x) film 6 b of the gateinsulating film 6 are simultaneously etched into substantially the sameshape as the signal line (24).

[0049] As shown with dashed, lines in FIG. 6, both ends, in the channelwidth direction, of the etching stopper 12 are removed through theetching.

[0050] As a result of the plasma etching, the source/drain electrodeunder layer 16, the etching stopper 12, the channel layer 8 and theSiN_(x) film 6 b are formed at substantially right angles to thetransparent substrate 2 or they are tapered in that order. Thus, thetilt angle of both side surfaces of the etching stopper 12 is generallydifferent.

[0051] In FIG. 5(d), Cs and Pa indicate a storage capacity portion and apad portion, respectively. As shown in FIGS. 5(a) and 5(b), aninter-layer insulating film on the intersection portion 5 a of thesignal line (24) and the gate line 5 has a laminated structure includinggate insulating films 6 (e.g., 6 a, 6 b) and channel layer 8.Thereafter, a transparent conductive film of indium-tin oxide (ITO) orthe like, functioning as a pixel electrode layer is formed on the entiresurface of the substrate 2.

[0052] Referring to FIG. 7, pixel electrode layers 18 having apredetermined shape are formed by a known method comprising the steps ofcoating of a photoresist, stepper exposure, development of thephotoresist, and wet etching, and then removing the photoresist.

[0053] As shown in FIGS. 8, 9(a) and 9(b), conductive metal is thendeposited to form the signal line 24, the source electrode 26, the drainelectrode 28, and the like. The conductive metal includes one or morelayers of one or more metals having good conductivity. Preferably, theconductive metal is a lamination including a Mo layer, an Al layer andanother Mo layer. However, the invention is not limited to thiscombination.

[0054] After forming one or more layers of the conductive metal byevaporation or the like, the steps of coating of a resist, stepperexposure and development of the resist are successively carried out inthe same manner as described above. Then, the conductive metal is etchedby a wet etching method to form the signal line 24, the source electrode26, the drain electrode 28 and the like.

[0055] Thereafter, the exposed source/drain electrode under layer 16,between the source electrode 26 and the drain electrode 28, is etched byplasma etching. In this plasma etching, the source/drain electrode underlayer 16 of n⁺ type a-Si is etched as shown in FIG. 10. However, thechannel layer 8 can be prevented from being etched by the etchingstopper 12 of SiN_(x). Thereafter, a liquid crystal display panel ismanufactured by a known method.

[0056] In the aforementioned manufacturing method, the etching stopper12 is formed only by exposing light to the substrate 2 from its backsurface by using the gate electrode 4 and the gate line 5 as shieldingmasks, as described with reference to FIGS. 3(a) and 3(b).

[0057] The manufacturing method of the present invention includes oneexposure step less than a conventional manufacturing method. In theconventional method having an exposing step using a reticle as ashielding mask, a high precision positioning of the shielding mask isrequired, which is a time-consuming task. Therefore, in themanufacturing method of the present invention, which includes oneexposure step less than the conventional method, productivity and yieldsare dramatically increased, and quality can be stabilized.

[0058] In addition, since the resist for forming the etching stopper isformed on the entire surface of the gate electrode 4 and the gate line5, and a bonded area of the resist formed by the present method islarger than that of a resist formed by a conventional method, the resistof the invention can hardly be peeled-off. Hence, an area of thephotoresist for forming the etching stopper 12 is small in theconventional method, and therefore more likely to be peeled-off.

[0059] However, in the present method, a photoresist is formed on theentire surface of the gate electrode 4 and the gate line 5, therebydecreasing the probability of poor formation of resists and thereforedecreasing the occurrence rate of defective transistors. Furthermore,since high-priced reticles are not used in the method of the presentinvention, the production cost can be sharply reduced.

[0060] Furthermore, the etching stopper 10 on the intersection portion 5a of the gate line 5 where the gate line 5, and the signal line 24intersect each other, is removed by being side-etched in a wet-etchingprocess. For this reason, etching solution does not penetrate throughthe signal line 24, and therefore damage to the signal line 24 can beprevented.

[0061] Further, as described with reference to FIGS. 5(a) to 5(d) andFIG. 6, both end portions of the etching stopper 12, having a nearlyidentical shape with the gate electrode 4 and the gate line 5, areremoved concurrently with the formation of the source/drain electrodeunder layer 16. For this reason, in an etching step of etching stopperlayer 10, as shown in FIG. 6, even when excessive overetching produces aconcavity 15 in the shape of an inverse taper, the concavity 15spreading over the source electrode 26 and the drain electrode 28 can beremoved by being etched.

[0062] As a result, since no leakage occurs between the source electrode26 and the drain electrode 28, the performance and the quality can beimproved. Moreover, the defect rate of products can be significantlyreduced.

[0063] A preferred embodiment of the liquid crystal display panel andthe method for manufacturing the same according to the present inventionhas thus been described above. However, the present invention is notlimited to the above embodiment.

[0064] For example, as shown in FIG. 11(a), opening portions 40 formedon the intersection portion 38 of the gate line 36 where the gate line36, and the signal line 24 intersect each other, can be a combination oflong slits and short slits, and each end of the opening portions 40 canoverlap one another. In this arrangement, even if the conductiveportions 42 are down, the electricity can be secured.

[0065] Also, as shown in FIG. 11(b), opening portions 44 formed on theintersection portion 38 of the gate line 36 where the gate line 36 andthe signal line 24 intersect each other, can have a circular shape. Thecircular opening portions 44 have sizes such that the photoresist can beremoved in the developing step, the etching stopper layer can bewet-etched through the circular holes formed in the developing step, andthe etching stopper layer in the vicinity of opening portions 44 can beside-etched. Accordingly, the opening portions 44 are not limited tocircles but can be any shape such as triangles, squares, pentagons,hexagons, ovals, oblongs or irregular shapes.

[0066] Furthermore, as shown in FIG. 11(c), if the width of the gateline 46 is too narrow to form opening portions 48, it is possible towiden the width of the intersection portion 50.

[0067] Further, the resist is not limited to a wet-type, but may be afilm-like resist. The wet-type resist is formed into film by a coatingor spraying method. The film-like resist is thermally compressed. Inaddition, the resist may be either a negative-type or positive-type.However, a form of shielding mask is reversed in accordance with theresist-type to be employed.

[0068] Further, the etching method can be suitably selected according toa material to be etched, but either one of wet-etching or dry-etchingcan be employed. The dry-etching method is not limited toplasma-etching, but can include chemical gas phase etching such asreactive ion etching, ion beam etching or reactive ion beam etching, orother kinds of etching.

[0069] The shielding mask may be a mask formed for a one-time exposurestep, but it may also be a reticle type which can be used for repeatedexposure steps by moving the mask (e.g., stepper exposure). A suitableshielding mask is used in consideration of factors related toproductivity, production cost, availability, and so forth.

[0070] A transparent substrate is used as the substrate. However, it isnot limited to a flat substrate, but may be a curved substrate. Inaddition, various changes, alterations and modifications may be made tothe embodiments by those skilled in the art without departing from thespirit and the scope of the present invention.

[0071] In the liquid crystal display panel and the method formanufacturing the same according to the present invention, the exposingstep of the etching stopper layer includes a single step in which thegate electrode and the gate line are used as shielding masks. Since themanufacturing method for the present invention does not include atime-consuming exposing step in which a shielding mask, such as areticle, is used and a high precision positioning of the shielding maskis required, productivity is dramatically increased.

[0072] Preferably, the etching stopper layer on the intersection portionof the gate line where the gate line, and the signal line intersect eachother, is removed by being side-etched by the opening portions formed onthe gate line. For this reason, etching solution, or the like, does notpenetrate through the signal line, and therefore the signal line cannotbe broken down easily.

[0073] In addition, since the resist for forming the etching stopper isformed on the entire surface of the gate electrode 4 and the gate line5, and a bonded area of the resist formed by the present method islarger than that of resist formed by a conventional method, the poorformation of resists and the occurrence rate of defective transistorsare decreased. Furthermore, since high-priced reticles are not used inthe method of the present invention, the production cost can be sharplyreduced.

[0074] Furthermore, since both end portions of the etching stopper,which is formed in the channel direction, are removed concurrently withthe formation of the source/drain electrode under the layer, even whenexcessive overetching produces a concavity in the shape of an inversetaper in an etching step of an etching stopper layer, the concavityspreads over the source electrode and the drain electrode can be removedby etching. As a result, since no leakage occurs between the sourceelectrode and the drain electrode, the performance and the quality canbe improved. Thus, the rate of defective products can be significantlyreduced.

[0075] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

What is claimed is:
 1. A liquid crystal display panel, comprising: agate line; and a signal line intersecting said gate line at anintersection portion, wherein said gate line comprises at least twoconductive portions and at least one opening portion on saidintersection portion where the gate line and the signal line intersecteach other.
 2. The liquid crystal display panel according to claim 1,wherein said at least one opening portion on the intersection portion ofthe gate line has a slit shape.
 3. The liquid crystal display panelaccording to claim 1, wherein said at least two conductive portions onthe intersection portion of the gate line are approximately 4 μm or lessin width.
 4. The liquid crystal display panel according to claim 2,wherein said at least two conductive portions on the intersectionportion of the gate line are approximately 4 μm or less in width.
 5. Aliquid crystal display panel comprising: a substrate; a gate electrodeformed on said substrate; a gate line connected to said gate electrode;a gate insulating film, a channel layer, and an etching stopper formedon said substrate; and a source/drain electrode and a signal line formedon said etching stopper, wherein two pairs of opposite side surfaces ofsaid etching stopper are inclined at different angles, and said gateline comprises at least two conductive portions and at least one openingportion on an intersection portion where the gate line and the signalline intersect each other.
 6. A liquid crystal display panel,comprising: a substrate; a gate electrode formed on said substrate; agate line connected to said gate electrode; a gate insulating film, achannel layer, and an etching stopper formed on said substrate; and asource/drain electrode and a signal line formed on said etching stopper,wherein at least one side surface of said etching stopper is atsubstantially right angles or tapered against the substrate, and saidgate line comprises at least two conductive portions and at least oneopening portion on an intersection portion where the gate line and thesignal line intersect each other.
 7. A liquid crystal display panel,comprising: a substrate; a gate electrode formed on said substrate; agate line connected to said gate electrode; a gate insulating film, achannel layer, and an etching stopper formed on said substrate; and asource/drain electrode and a signal line formed on said etching stopper,wherein at least one side surface of said etching stopper extendingperpendicularly to current flow is at substantially right angles ortapered against the substrate, and said gate line comprises at least twoconductive portions and at least one opening portion on an intersectionportion where the gate line and the signal line intersect each other. 8.A liquid crystal display panel, comprising: a substrate; a gateelectrode formed on said substrate; a gate line connected to said gateelectrode; a gate insulating film, a channel layer, and an etchingstopper formed on said substrate; and a source/drain electrode and asignal line formed on said etching stopper, wherein at least saidetching stopper and said source/drain electrode under layer aresimultaneously etched, and said gate line comprises at least twoconductive portions and at least one opening portion on an intersectionportion where the gate line and the signal line intersect each other. 9.The liquid crystal display panel according to claim 5, wherein a SiNxfilm is formed between said gate insulating film and said channel layer.10. The liquid crystal display panel according to claim 6, wherein aSiNx film is formed between said gate insulating film and said channellayer.
 11. The liquid crystal display panel according to claim 7,wherein a SiNx film is formed between said gate insulating film and saidchannel layer.
 12. The liquid crystal display panel according to claim8, wherein a SiNx film is formed between said gate insulating film andsaid channel layer.
 13. The liquid crystal display panel according toclaim 1, further comprising a gate insulating film, wherein said gateinsulating film is made from SiOx or SiNx.
 14. The liquid crystaldisplay panel according to claim 1, further comprising a gate electrode,wherein said gate electrode and said gate line comprise at least onelayer of at least one element selected from the group consisting of MoW,Cr, Cu, Ni, Al, Mo, and Ag.
 15. A method for manufacturing a liquidcrystal display panel, comprising: forming a gate electrode and a gateline on a transparent substrate, wherein said gate line comprises atleast two conductive portions and at least one opening portion on anintersection portion where said gate line and said signal line intersecteach other; forming a gate insulating film on an entire surface of saidsubstrate; forming a channel layer on said gate insulating film; formingan etching stopper layer on said channel layer; forming a resist film onsaid etching stopper layer; exposing the substrate to light from itsback surface by using the gate electrode and the gate line as shieldingmasks; developing said resist film; etching said etching stopper layer,and at the same time, side-etching the etching stopper layer portion inan upper vicinity of the at least one opening portion of the gate line;and removing said resist film.
 16. The method for manufacturing a liquidcrystal display panel according to claim 15, wherein said etching theetching stopper layer comprises wet-etching the etching stopper layer byusing dilute fluoride acid.
 17. The method for manufacturing a liquidcrystal display panel according to claim 15, further comprising: forminga source/drain layer on an entire surface of the substrate; forming aresist on the source/drain layer; exposing the substrate to light;developing the resist; etching the source/drain layer and a remainingportion of the etching stopper layer through chemical gas phase etching;and removing the resist.
 18. The method for manufacturing a liquidcrystal display panel according to claim 17, wherein said source/drainlayer is made from an n⁺ type a-Si layer.
 19. The method formanufacturing a liquid crystal display panel according to claim 17,wherein said exposing the substrate to light comprises conducting astepper exposure by using a reticle.
 20. The method for manufacturing aliquid crystal display panel according to claim 17, further comprising:forming a transparent electrode on said substrate; and forming saidsignal line on said substrate.
 21. The method for manufacturing a liquidcrystal display panel according to claim 16, wherein said signal line ismade from a lamination including a Mo layer, an Al layer, and a secondMo layer.